// simple Register
module SimReg #(DATA_LEN = 1, RST_V = 0) (
  input clk,
  input rst,
  input [DATA_LEN-1:0] in,
  output reg [DATA_LEN-1:0] out,
  input wen
);

  always @(posedge clk or wen) begin
    if (rst)
      out <= RST_V;
    else begin
      if (wen) begin
        out <= in;
      end
      else
        out <= out;
    end
  end

endmodule
